The invention relates to a method for fabricating a semiconductor on insulator (SeOI) substrate, in particular a silicon on insulator (SOI) substrate, that has a reduced density of Secco Defects. The method generally comprises the steps of providing a source substrate, providing a predetermined splitting area inside the source substrate, attaching, preferably by bonding, the source substrate to a handle substrate, detaching a remainder of the source substrate from the source handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. The implanting and thinning steps are conducted under controlled conditions such that the thinned device layer exhibits a reduced Secco Defect Density. The term “device layer” and “transfer layer” are used interchangeably herein to designate a layer which is part of the source substrate that is transferred to the handle substrate and in which electronic devices or other components can be formed.
Such semiconductor on insulator substrates, like the mentioned silicon on insulator substrates, typically present a certain amount of different defects, e.g., crystalline defects, point defects, metallic contamination, etc. One particular type of defect is a so-called Secco defect. In the past, these defects were not considered to be critical as the number of such defects was sufficiently low for typical SOI applications, e.g., supporting logic circuits. Today, however, new applications are being developed for SeOI and SOI technology, e.g., memory devices, such that the SeOI substrates need to present much lower Secco defects than in the past. In particular, the Secco defect density should be less than 100 per cm2, whereas, up to now, this value was higher by a factor of about five.
FIG. 1 illustrates the standard process of determining Secco defects in SOI structures. This process has been further described in L. F. Giles, A. Nejim, P. L. F. Hemment, Vacuum 43, 297 (1992) or by the same authors in Materials Chemistry and Physics 35 (1993) 129-133. The concentration of Secco defects can be determined by displaying them by virtue of a solution of Secco type, the composition of which is known from the above mentioned documents. Starting from a SOI substrate 1 comprising a device layer 3 with a thickness of e.g., 2000 Å and a silicon oxide layer 5 with a thickness of e.g., 4000 Å on a silicon wafer 7, a standard technique for displaying defects by virtue of a solution of Secco type comprises the steps that are now described.
A first stage (A) requires immersing the substrate 1 for several seconds, for example 10 to 25 seconds, in a solution of Secco type in order to etch 1000 to 2000 Å of silicon from the device layer 3 and more rapidly to selectively etch this device layer 3 at the crystal defects 9 in the material until holes 11 corresponding to the sites of the defects 9 open onto the silicon oxide layer 5. The duration of stage A depends on the thickness to be removed and has to be such that all Secco defects can be identified. As a rule of thumb, at least half of the thickness of the device layer is removed, but for thicker layers this might be much more, even as much as 85% of the thickness is removed. For example, 300 to 500 Angstroms of thickness can remain, even for device layers that originally have a thickness between 1000 and 2000 Angstroms. On the other hand, for very thin device layers (800 Angstroms or even less than 500 Angstroms), it might be sufficient to remove less than half of that thickness because all Secco defects are revealed at that point, i.e., the Secco defects penetrate the device layer even before half of the thickness is etched away.
A second stage (B) requires immersing the substrate 1 in a hydrofluoric acid solution in order to etch the holes 11 produced in the preceding stage, by widening them in the dielectric layer 5. Following this treatment, the holes 11 which remain are sufficiently large so that they can be counted under a microscope. It appears that, at a certain remaining device layer 3 thickness, the defect density stabilizes and reaches an upper limit value indicating that, starting from this thickness, all defects in the original layer are visualized. In the case of standard semiconductor on insulator substrates, stabilization is achieved around 500 Å or at the latest when around 300 Å of device layer 3 thickness remains. Indeed, it appears that the device layer 3 in the zone of Secco defects etches approximately twice as fast as the normal device layer in zones without Secco defects.
US 2005/0208322 discloses a method for fabricating a semiconductor on insulator substrate dealing with removal of defects. The proposed process is a SmartCut® type process which comprises additional steps to transfer a semiconductor device layer from a source substrate onto a handle substrate to reduce the number of defects. These additional steps comprise a sacrificial oxidation stage transforming a part of the device layer into an oxide, which is removed, followed by a polishing stage. With the implementation of these additional steps, defects in the surface regions can be removed. However, the polishing stage introduces additional defects which are then removed by a second sacrificial oxidation stage oxidizing a surface part of the semiconductor device layer and removing the oxidized portions. With this method, Secco defects in a range of about 500 defects per cm2 can be achieved. This method is not desirable as it has the disadvantage that an additional process step is necessary and, furthermore, that it is not possible to achieve the new requirements for defect levels of 100 defects per cm2 or lower.
Other SOI manufacturing processes have been proposed which do not include the additional polishing step. US 2005/0026426 proposes a thermal treatment to minimize high frequency roughness so that chemical mechanical polishing is not needed. This type of process, in particular, includes a high temperature anneal of the silicon on insulator substrate with the device layer being protected by a layer of silicon oxide, a technique known as “stabilization oxidation anneal”. However, this type of long and high temperature anneal can generate other types of defects such as slip lines. Furthermore, these kind of anneal steps require furnaces that can sustain high temperatures which are generally relatively expensive and difficult to control in terms of contamination.
It appears that these known processes are not suitable to reduce Secco defect densities to lower than 100 per cm2 and that, for device layers of less than 1000 Å, the described methods do not lead to satisfying results. Now, however, the present invention provides a semiconductor on insulator wafer fabrication method that produces a Secco defect density of less than 100 defects per cm2 and the method can be applied to relatively thin device layers to overcome the shortcomings of the prior art.